module trans_data
#(
parameter  SYNC1=10'b1010_1010_10,   //preamble---前导字
parameter  SYNC2=10'b1010_1010_11
)
(

input				rst,
input				clk_10M,
input				clk_100M,

input				tx_vld,
input				tx_done,
input				ki,
input	[7:0]		tx_data,
output			tx_out



);










wire	[9:0]  enc_data_out;

enc_8b10b_s  enc_8b10b_s_inst
(
.clk_10M			(clk_10M),
.rst				(rst),

.ki				(ki),
.data_in			(tx_data),

.data_out		(enc_data_out)  //10bit--

);



lvds_tx_pack
#(
.SYNC1(SYNC1),
.SYNC2(SYNC2)
)
lvds_tx_pack_inst
(

.rst			(rst),
.clk_10M		(clk_10M),
.clk_100M	(clk_100M),
.tx_vld		(tx_vld),
.tx_data		(enc_data_out),
.tx_done		(tx_done),
.tx_out		(tx_out)


);



endmodule
